Harish, BP and Bhat, Navakanta (2006) Resistive Modeling of Estimation of Static Leakage Power in Nanoscale CMOS. In: IMAPS India National Conference, , December 2006, Hyderabad.
Full text not available from this repository. (Request a copy)Item Type: | Conference Paper |
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Department/Centre: | Division of Electrical Sciences > Electrical Communication Engineering |
Date Deposited: | 11 Nov 2011 06:42 |
Last Modified: | 11 Nov 2011 06:42 |
URI: | http://eprints.iisc.ac.in/id/eprint/42039 |
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