A Scalable Low Power Issue Queue for Large Instruction Window Processors

Vivekanandham, Rajesh and Amrutur, Bharadwaj and Govindarajan, R (2006) A Scalable Low Power Issue Queue for Large Instruction Window Processors. In: ICS '06 Proceedings of the 20th annual international conference on Supercomputing , June 2006, Cairns, Australia.

PDF A_Scalable.pdf - Published Version Restricted to Registered users only Download (1MB) | Request a copy

Abstract

Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order superscalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.To address both these issues comprehensively, we propose the Scalable Lowpower Issue Queue (SLIQ). SLIQ augments a pipelined issue queue with direct indexing to mitigate the problem of delayed wakeups while reducing the cycle time. Also, the SLIQ design naturally leads to significant energy savings by reducing both the number of tag broadcasts and comparisons required.A 2 segment SLIQ incurs an average IPC loss of 0.2% over the entire SPEC CPU2000 suite, while achieving a 25.2% reduction in issue latency when compared to a monolithic 128-entry issue queue for an 8-wide superscalar processor. An 8 segment SLIQ improves scalability by reducing the issue latency by 38.3% while incurring an IPC loss of only 2.3%. Further, the 8 segment SLIQ significantly reduces the energy consumption and energy-delay product by 48.3% and 67.4% respectively on average.

Item Type:	Conference Paper
Publisher:	ACM Press
Additional Information:	Copyright of this article belongs to ACM Press.
Keywords:	issue logic;wakeup logic;low-power architecture;complexity- effective architecture
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	10 Nov 2011 05:49
Last Modified:	10 Nov 2011 05:49
URI:	http://eprints.iisc.ac.in/id/eprint/41963

Actions (login required)

View Item