Rajan, Kaushik and Ramaswamy, Govindarajan (2007) Emulating Optimal Replacement with a Shepherd Cache. In: MICRO 40 Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC.
![]() |
PDF
Emulating.pdf - Published Version Restricted to Registered users only Download (532kB) | Request a copy |
Abstract
The inherent temporal locality in memory accesses is filtered out by the L1 cache. As a consequence, an L2 cache with LRU replacement incurs significantly higher misses than the optimal replacement policy (OPT). We propose to narrow this gap through a novel replacement strategy that mimics the replacement decisions of OPT. The L2 cache is logically divided into two components, a Shepherd Cache (SC) with a simple FIFO replacement and a Main Cache (MC) with an emulation of optimal replacement. The SC plays the dual role of caching lines and guiding the replacement decisions in MC. Our pro- posed organization can cover 40% of the gap between OPT and LRU for a 2MB cache resulting in 7% overall speedup. Comparison with the dynamic insertion policy, a victim buffer, a V-Way cache and an LRU based fully associative cache demonstrates that our scheme performs better than all these strategies.
Item Type: | Conference Paper |
---|---|
Publisher: | ACM Press |
Additional Information: | Copyright of this article belongs to ACM Press. |
Department/Centre: | Division of Electrical Sciences > Computer Science & Automation Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre |
Date Deposited: | 19 Oct 2011 07:04 |
Last Modified: | 19 Oct 2011 07:04 |
URI: | http://eprints.iisc.ac.in/id/eprint/41520 |
Actions (login required)
![]() |
View Item |