A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors

Vivekanandham, Rajesh and Govindarajan, R (2007) A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors. In: Poster session at the Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT-2007), September 15--19, 2007, Brasov, Romania.

Full text not available from this repository. (Request a copy)

Item Type:	Conference Paper
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	17 Oct 2011 05:25
Last Modified:	17 Oct 2011 05:25
URI:	http://eprints.iisc.ac.in/id/eprint/41458

Actions (login required)

View Item