ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS

Harish, BR and Bhat, Navakanta and Patil, Mahesh B (2007) Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS. In: SISPAD, Vienna, Austria, Vienna, Austria.

[img] PDF
Process_Variation.pdf - Published Version
Restricted to Registered users only

Download (240kB) | Request a copy
Official URL: http://www.springerlink.com/content/w8956120426731...


We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.

Item Type: Conference Poster
Publisher: Springer
Additional Information: Copyright of this article belongs to Springer.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 13 Oct 2011 07:35
Last Modified: 13 Oct 2011 07:35
URI: http://eprints.iisc.ac.in/id/eprint/41387

Actions (login required)

View Item View Item