Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

Fell, Alexander and Alle, Mythri and Varadarajan, Keshavan and Biswas, Prasenjit and Das, Saptarsi and Chetia, Jugantor and Nandy, SK and Narayan, Ranjani (2009) Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration. In: proceedings of the 2009 International Conference on Compilers,Architecture and Synthesis for Embedded Systems (CASES 2009),, Grenoble,Frane.

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Abstract

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

Item Type:	Conference Paper
Publisher:	ACM, Inc.
Additional Information:	Copyright of this article belongs to ACM, Inc.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	13 Dec 2011 11:50
Last Modified:	13 Dec 2011 11:50
URI:	http://eprints.iisc.ac.in/id/eprint/41285

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