ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip

Choudhary, Naveen and Gaur, MS and Laxmi, Vijay and Singh, Virendra (2009) Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip. In: IEEE INDICON 2009, 18-20 Dec. 2009, Gujarat.

[img] PDF
Conjoined.pdf - Published Version
Restricted to Registered users only

Download (232kB) | Request a copy
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...


Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for multi media communication applications. The heterogeneous nature of application specific on-chip cores along with the specific communication requirements among the cores calls for the design of application-specific NoCs for improved performance in terms of communication energy, latency, and throughput. In this work, we propose a methodology for the design of customized irregular networks-on-chip. The proposed method exploits a priori knowledge of the applications communication characteristic to generate an optimized network topology and corresponding routing tables.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 13 Dec 2011 12:00
Last Modified: 13 Dec 2011 12:00
URI: http://eprints.iisc.ac.in/id/eprint/41278

Actions (login required)

View Item View Item