ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

FREP: A Soft-Error Resilient Pipelined RISC Architecture

Kumar, V and Choudhary, RR and Singh, V (2009) FREP: A Soft-Error Resilient Pipelined RISC Architecture. In: IEEE East-West Design and Test Symposium (EWDTS) 2009, Sep 2009, Moscow, Russia.

[img] PDF
FREP.pdf - Published Version
Restricted to Registered users only

Download (386kB) | Request a copy
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...


Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 13 Dec 2011 12:04
Last Modified: 13 Dec 2011 12:04
URI: http://eprints.iisc.ac.in/id/eprint/41272

Actions (login required)

View Item View Item