An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors

Menon, Sreejith K and Shankar, Priti (2005) An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors. In: DCC 2005 Data Compression Conference, 2005, 29-31 March, Utah, p. 470.

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Abstract

We propose a general purpose code compression scheme for embedded systems, based on the instruction set architecture and report results on the Intel StrongARM, a low-cost, low-power RISC architecture and TI TMS320C62x, a widely used VLIW architecture. Fast decompression techniques are explored to improve the decompression overhead of the compression scheme. Compression ratios ranging from 68% to 75% were obtained for TMS320C62x and 69% to 78% for the StrongARM processor. The basic idea of the compression scheme is to divide the instructions into different logical classes and to build multiple dictionaries for them. The size and the number of multiple dictionaries are fixed for a given processor and are determined by the partitioning algorithm which works over the instruction set architecture supplied as input. Frequently occurring unique instruction segments are inserted into the dictionaries and the instructions are encoded as pointers to the respective entries. An opcode, which helps in fast decompression, is attached to an instruction segment to identify its logical class and the dictionary to be accessed.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	23 Nov 2005
Last Modified:	19 Sep 2010 04:21
URI:	http://eprints.iisc.ac.in/id/eprint/4085

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