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Dynamically Reconfigurable Regular Expression Matching Architecture

Divyasree, J and Rajashekar, H and Varghese, Kuruvilla (2008) Dynamically Reconfigurable Regular Expression Matching Architecture. In: 20th IEEE International Conference on Application-specific Systems, Architectures and Processors 2008 (ASAP 2008), 2-4 July 2008, Leuven.

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Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Nondeterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further,we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 17 Oct 2011 06:44
Last Modified: 17 Oct 2011 06:44
URI: http://eprints.iisc.ac.in/id/eprint/40647

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