In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

Mehta, Nandish and Naik, Gururaj and Amrutur, Bharadwaj (2010) In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 18-20 Aug. 2010, Austin, TX, USA.

PDF In-Situ.pdf - Published Version Restricted to Registered users only Download (1MB) | Request a copy

Abstract

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 2010 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	20 Dec 2011 08:27
Last Modified:	20 Dec 2011 08:27
URI:	http://eprints.iisc.ac.in/id/eprint/38961

Actions (login required)

View Item