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Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

Ramanathan, S and Visvanathan, V (1999) Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay. In: Integration, the VLSI Journal, 27 (1). pp. 1-32.

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Official URL: http://dx.doi.org/10.1016/S0167-9260(98)00013-3


The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.

Item Type: Journal Article
Publication: Integration, the VLSI Journal
Publisher: Elsevier Science
Additional Information: Copyright of this article belongs to Elsevier Science.
Keywords: Adaptive filtering;Least mean squares algorithm;Low power; Pipelined architectures;Systolic architectures;Configurable processor array
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 23 Jun 2011 09:55
Last Modified: 23 Jun 2011 09:55
URI: http://eprints.iisc.ac.in/id/eprint/38603

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