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Pipelined ring algorithm for matrix multiplication on transputer networks: performance analysis and estimation

Srinivas, S and Basu, A and Kumar, KG and Paulraj, A and Patnaik, LM (1992) Pipelined ring algorithm for matrix multiplication on transputer networks: performance analysis and estimation. In: Computer Systems Science and Engineering, 7 (1). pp. 42-51.

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Official URL: http://portal.acm.org/citation.cfm?id=176474


A parallel matrix multiplication algorithm is presented, and studies of its performance and estimation are discussed. The algorithm is implemented on a network of transputers connected in a ring topology. An efficient scheme for partitioning the input matrices is introduced which enables overlapping computation with communication. This makes the algorithm achieve near-ideal speed-up for reasonably large matrices. Analytical expressions for the execution time of the algorithm have been derived by analysing its computation and communication characteristics. These expressions are validated by comparing the theoretical results of the performance with the experimental values obtained on a four-transputer network for both square and irregular matrices. The analytical model is also used to estimate the performance of the algorithm for a varying number of transputers and varying problem sizes. Although the algorithm is implemented on transputers, the methodology and the partitioning scheme presented in this paper are quite general and can be implemented on other processors which have the capability of overlapping computation with communication. The equations for performance prediction can also be extended to other multiprocessor systems.

Item Type: Journal Article
Publication: Computer Systems Science and Engineering
Publisher: CRL Publishing
Additional Information: Copyright of this article belongs to CRL Publishing.
Keywords: Distributed Memory Multiprocessors;Matrix Multiplication; Message Passing;Performance Analysis;Performance Estimation; Pipelined Ring Algorithm;Transputer Networks.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 02 May 2011 05:14
Last Modified: 02 May 2011 05:14
URI: http://eprints.iisc.ac.in/id/eprint/37328

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