Toward Effective Scalar Hardware for Highly Vectorizable Applications

S, Vajapeyam and WC, Hsu (1993) Toward Effective Scalar Hardware for Highly Vectorizable Applications. In: Journal of Parallel and Distributed Computing, 19 (3). 147-162 .

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Abstract

The performance of a program will ultimately be limited by its serial (scalar) portion, as pointed out by Amdahl′s Law. Reported studies thus far of instruction-level parallelism have mixed data-parallel program portions with scalar program portions, often leading to contradictory and controversial results. We report an instruction-level behavioral characterization of scalar code containing minimal data-parallelism, extracted from highly vectorized programs of the PERFECT benchmark suite running on a Cray Y-MP system. We classify scalar basic blocks according to their instruction mix, characterize the data dependencies seen in each class, and, as a first step, measure the maximum intrablock instruction-level parallelism available. We observe skewed rather than balanced instruction distributions in scalar code and in individual basic block classes of scalar code; nonuniform distribution of parallelism across instruction classes; and, as expected, limited available intrablock parallelism. We identify frequently occurring data-dependence patterns and discuss new instructions to reduce latency. Toward effective scalar hardware, we study latency-pipelining trade-offs and restricted multiple instruction issue mechanisms.

Item Type:	Journal Article
Publication:	Journal of Parallel and Distributed Computing
Publisher:	Elsevier Science
Additional Information:	Copyright of this article belongs to Elsevier Science.
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	14 Mar 2011 08:42
Last Modified:	14 Mar 2011 08:42
URI:	http://eprints.iisc.ac.in/id/eprint/35955

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