Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help

Mannarswamy, Sandya and Govindarajan, R (2010) Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help. In: 19th International Conference on Parallel Architectures and Compilation Techniques, SEP 11-15, 2010, Austrian Acad Sci Vienna, Vienna, AUSTRIA,, pp. 547-548.

PDF Analyz.pdf - Published Version Restricted to Registered users only Download (378kB) | Request a copy

Abstract

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.

Item Type:	Conference Paper
Publisher:	Assoc Computing Machinery
Additional Information:	Copyright of this article belongs to Assoc Computing Machinery.
Keywords:	cache; software transactional memory; compiler
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	07 Mar 2011 08:39
Last Modified:	07 Mar 2011 08:39
URI:	http://eprints.iisc.ac.in/id/eprint/35908

Actions (login required)

View Item