On Minimization of Test Application Time for RAS

Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K and Fujiwara, Hideo and Singh, Adit D (2010) On Minimization of Test Application Time for RAS. In: 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems, JAN 03-07, 2010, Bangalore, India, pp. 393-398.

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Abstract

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 2010 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	29 Nov 2010 11:28
Last Modified:	29 Nov 2010 11:28
URI:	http://eprints.iisc.ac.in/id/eprint/34071

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