Ravikumar, PC and Sastry, S and Patnaik, LM (1991) Parallel min-cut placement on reduced hardware SIMD architecture. In: Computer Systems Science and Engineering, 6 (1). 3 -12.
Full text not available from this repository. (Request a copy)Abstract
Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.
| Item Type: | Journal Article |
|---|---|
| Publication: | Computer Systems Science and Engineering |
| Publisher: | CRL Publishing |
| Additional Information: | Copyright of this article belongs to CRL Publishing. |
| Keywords: | Massively Parallel Computing;Data Parallel Algorithms;Simd Architecture;Vlsi Circuit Partitioning;Vlsi Placement; Min-Cut Placement. |
| Department/Centre: | Division of Electrical Sciences > Computer Science & Automation |
| Date Deposited: | 26 Nov 2010 05:24 |
| Last Modified: | 26 Nov 2010 05:24 |
| URI: | http://eprints.iisc.ac.in/id/eprint/34034 |
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