An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning

Bondada, Sivakumar and Raha, Soumyendu and Mahapatra, Santanu (2010) An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning. In: Sadhana : Academy Proceedings in Engineering Sciences, 35 (4). pp. 407-418.

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Abstract

In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect-networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as correlated Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Function (PDF) at all nodes in the interconnect network. Main objective is to find delay PDF at a cheaper cost. Convergence of this approach is in probability distribution but not in mean of delay. We validate our approach against SPICE based Monte Carlo simulations while the current method entails significantly lower computational cost.

Item Type:	Journal Article
Publication:	Sadhana : Academy Proceedings in Engineering Sciences
Publisher:	Indian Academy of Sciences
Additional Information:	Copyright of this article belongs to Indian Academy of Sciences.
Keywords:	Statistical timing analysis; VLSI clock interconnects; delay variability; PDF; process variation; Gaussian random variation; computational cost.
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	26 Oct 2010 06:56
Last Modified:	26 Oct 2010 06:56
URI:	http://eprints.iisc.ac.in/id/eprint/33403

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