Architecture of Run-time Reconfigurable Channel Decoder

Rajore, Ritesh and Nandy, SK and Jamadagni, HS (2009) Architecture of Run-time Reconfigurable Channel Decoder. In: IEEE International Conference on Communications (ICC 2009), JUN 14-18, 2009, Dresden, pp. 2961-2966.

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Abstract

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Item Type:	Conference Paper
Series.:	IEEE International Conference on Communications
Publisher:	IEEE
Additional Information:	Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	08 Sep 2010 08:26
Last Modified:	19 Sep 2010 06:15
URI:	http://eprints.iisc.ac.in/id/eprint/32038

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