A cost effective pipelined divider for double precision floating point number

Singh, Sandeep B and Biswas, Jayanta and Nandy, SK (2006) A cost effective pipelined divider for double precision floating point number. In: 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Steamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 132-137.

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Abstract

he growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency; pipelined floating point dividers. Solutions available in the literature use large lookup table for double precision floating point operations.In this paper, we propose a cost effective, fixed latency pipelined divider using modified Taylor-series expansion for double precision floating point operations. We reduce chip area by using a smaller lookup table. We show that the latency of the proposed divider is 49.4 times the latency of a full-adder. The proposed divider reduces chip area by about 81% than the pipelined divider in [9] which is based on modified Taylor-series.

Item Type:	Conference Paper
Series.:	IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS
Publisher:	IEEE
Additional Information:	Copyright 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	31 Aug 2010 05:28
Last Modified:	22 Oct 2018 12:01
URI:	http://eprints.iisc.ac.in/id/eprint/30456

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