Design of A Generic CELP Architecture

Madhusudhan, S and Monga, S and Ramakrishna, STGS and Jamadagni, HS and Rao, Ashok (2002) Design of A Generic CELP Architecture. In: 6th IEEE VLSI Design and Test Workshop, Bangalore, India.

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Abstract

Modern mobile communications require optimum bandwidth utilization with minimum loss, delay and good quality of speech transmission. This triggered the usage of low bit rate voice Codecs among which CELP Codecs inherit the merits of both Waveform and Source codecs, like toll quality, low bit rate etc. In this paper an attempt has been made to form some special generic hardware blocks for the ITU G.729 standard (CS-ACELP, Conjugate Structure Algebraic Code Excited Linear Prediction) of 8Kbps bit rate CELP algorithm. This is aimed at overcoming the limitation of computational burden and also scaling this application for enhanced speed and extracting more number of channels.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	CS-ACELP;DSP;Parallelism;Pipelining
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	02 Feb 2007
Last Modified:	19 Sep 2010 04:18
URI:	http://eprints.iisc.ac.in/id/eprint/2703

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