ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Design of a synchronous decade down counter

Nagaraj, HS and Hariharan, R (1974) Design of a synchronous decade down counter. In: International Journal of Electronics, 36 (5). pp. 601-606.

Full text not available from this repository. (Request a copy)
Official URL: http://www.informaworld.com/smpp/content~db=all~co...


Digital positioning systems often require a down counter for their operation. Due to the necessity of particular logic sequences and control of individual terminals, the design of down counters for particular use is very essential. In this paper the design procedure and logic diagram for a synchronous decade down counter with parallel carry are presented.

Item Type: Journal Article
Publication: International Journal of Electronics
Publisher: Taylor and Francis Group
Additional Information: Copyright of this article belongs to Taylor and Francis Group.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 17 Dec 2009 06:27
Last Modified: 17 Dec 2009 06:27
URI: http://eprints.iisc.ac.in/id/eprint/23886

Actions (login required)

View Item View Item