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A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture

Biswas, NN and Srinivas, S and Dharanendra, Trishala (1987) A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture. In: ACM SIGARCH Computer Architecture News, 15 (1). pp. 81-87.


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The paper describes a multistage shuffle interconnection network which is controlled by a central monitor. A control code broadcast by the monitor to all the basic switching elements of the network simultaneously, makes the network dynamically reconfigurable. The control code plays three vital roles. Firstly, it establishes conflict-free paths between several source-destination pairs. Thus the problem of collision, a major obstacle of a self-routing network,is completely eliminated. Secondly, the direct paths are established in one clock period irrespective of the number of stages. This makes the system faster. Thirdly, the control code also acts as a grouping code for executing a table of arbitrary data exchange requests between nodes in minimum number of passes. It is also shown that the network can be made fault-tolerant by the addition of an extra stage. Any single fault and some multiple faults in the intermediate stages can be tolerated by this scheme. Moreover, the switching from the faulty state to the fault-free state can be done in a single clock period, thus enabling fast fault-tolerant reconfiguration.

Item Type: Journal Article
Publication: ACM SIGARCH Computer Architecture News
Publisher: ACM Press
Additional Information: © ACM,1987.This is the author's version of the work.It is posted here by permission of ACM for your personal use. Not for redistribution.The definitive version was published in ACM SIGARCH Computer Architecture News,VOL 15, ISS 1,March 1987 http://doi.acm.org/10.1145/25372.25382
Keywords: centrally controlled interconnection network;fault-tolerant architecture;inter-connection networks;multiprocessor systems;reconfigurable architecture;routing techniques;shuffle network
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 07 Jun 2004
Last Modified: 27 Feb 2019 09:01
URI: http://eprints.iisc.ac.in/id/eprint/237

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