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On-Chip Clock Network Skew Measurement using Sub-Sampling

Das, Pratap Kumar and Bharadwaj, Amrutur and Sridhar, J and Visvanathan, V (2008) On-Chip Clock Network Skew Measurement using Sub-Sampling. In: 4th IEEE Asian Solid-State Circuits Conference, NOV 03-05, 2008, Fukuoka, Japan.

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We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Circuits
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 03 Feb 2010 10:06
Last Modified: 19 Sep 2010 05:31
URI: http://eprints.iisc.ac.in/id/eprint/20012

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