ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

A Dual Five-Level Inverter-Fed Induction Motor Drive With Common-Mode Voltage Elimination and DC-Link Capacitor Voltage Balancing Using Only the Switching-State Redundancy—Part I

Tekwani, PN and Gopakumar, K (2007) A Dual Five-Level Inverter-Fed Induction Motor Drive With Common-Mode Voltage Elimination and DC-Link Capacitor Voltage Balancing Using Only the Switching-State Redundancy—Part I. In: IEEE Transactions on Industrial Electronics, 54 (5). pp. 2600-2608.

[img] PDF
A_Dual_Five-Level.pdf
Restricted to Registered users only

Download (756kB) | Request a copy

Abstract

For a dual five-level inverter-fed induction motor (IM) drive, effects of dc-neutral currents on dc-link capacitor voltage fluctuations are analyzed in this paper. Operating limitations in achieving the dual task of common-mode voltage elimination and dc-link capacitor voltage balancing with a single dc power supply are further investigated for the proposed drive. In this paper, an open-loop control scheme, which uses only the availability of redundant switching states for the inverter control, is presented. Limitation of proposed open-loop control to take corrective action for any existing unbalance in capacitor voltages calls for a closed-loop control scheme, which is presented in Part II of this paper.

Item Type: Journal Article
Publication: IEEE Transactions on Industrial Electronics
Publisher: IEEE
Additional Information: ©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Common-mode voltage (CMV) elimination, dc-link capacitor voltage balancing, induction motor (IM) drive, multilevel inverter, open-loop control, switching-state redundancy.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 30 Jul 2008
Last Modified: 19 Sep 2010 04:48
URI: http://eprints.iisc.ac.in/id/eprint/15372

Actions (login required)

View Item View Item