Sundaram, S and Patnaik, LM (1992) Logic simulation algorithm on network of transputers. In: Transputer/Occam. Japan 4. Proceedings of the 4th Transputer/Occam International Conference, 4-5 June 1992, Tokyo, Japan, pp. 219-230.
Full text not available from this repository. (Request a copy)Abstract
Explores the possibility of mapping a T-algorithm based logic simulation algorithm onto a network of transputers interconnected by high speed links. The set of gates at a particular level is partitioned by the master task (running on the root transputer) and communicated to the other transputers through the high speed links. The tasks running on other transputers (slave tasks) evaluate the set of gates assigned for the complete simulation period and communicate the evaluated output back to the master task. After receiving the evaluated output from all transputers, the master task partitions the gates at the next level and communicates this new set of gates for evaluation. The master transputer also participates in the evaluation process along with other transputers. This process is repeated for all the levels in the circuit. Two types of partitioning schemes have been implemented and their performance are also discussed. The distributed logic simulation algorithm has been implemented on a work of transputers using the communication primitives chan in and chan out provided by the 3Lc compiler. The paper concludes with a tabulated results on the speedup figures obtained on the ISCAS benchmark circuits
| Item Type: | Conference Paper |
|---|---|
| Publisher: | IOS Press |
| Additional Information: | Copyright of this article belongs to IOS Press. |
| Keywords: | circuit analysis computing;logic CAD;parallel algorithms; transputer systems |
| Department/Centre: | Division of Electrical Sciences > Electrical Communication Engineering |
| Date Deposited: | 11 Jan 2008 |
| Last Modified: | 12 Jan 2012 07:12 |
| URI: | http://eprints.iisc.ac.in/id/eprint/11139 |
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