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Simulation and performance evaluation of parallel architecture based on i860 nodes: SapePar-i860

Pandlan, A and Parthasarathy, K and Sridhar, MK and Gowda, KC (1994) Simulation and performance evaluation of parallel architecture based on i860 nodes: SapePar-i860. In: of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: `Frontiers of Computer Technology', 22-26 Aug. 1994, Singapore, pp. 682-686.

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SapePar-i860 is an execution driven “Simulator and Performance Evaluator for i860 based Parallel Architecture�?. The simulator has various inputs like the primary cache size, primary cache type, secondary cache size, secondary cache type, secondary cache replacement policy, number of processors, interconnection between the processors, communication path from each processor to other processors, type of communication and bandwidth of communication channels. The simulator gets configured automatically according to the inputs and generates log files. The performance analyzer generates statistics of the run based on these log files. The statistics includes cache hit ratio of primary cache, cache hit ratio of secondary cache, Complete Communication Ratio $(CCR_i)$ of each processor, the Compute Communication Ratio $(CCR_6)$ of overall system, efficiency of each processor and efficiency of overall system. This also computes the speedup, execution time in terms of clock ticks

Item Type: Conference Paper
Publisher: IEEE
Additional Information: 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE
Keywords: cache storage;parallel architectures;performance evaluation;virtual machines
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Date Deposited: 08 Nov 2007
Last Modified: 19 Sep 2010 04:38
URI: http://eprints.iisc.ac.in/id/eprint/11053

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