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A VLSI Architecture for the computation of NURBS Patches

Gopi, Meenakshi Sundaram and Manohar, Swami (1995) A VLSI Architecture for the computation of NURBS Patches. In: 8th International Conference on VLSI Design, 4-7 January 1995, New Delhi, India, pp. 326-331.


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B-Spline curves and patches are increasingly being used in several areas of computer graphics and geometric modeling. The rationalized counterpart of B-spline called Non-Uniform Rational B-Spline (NURBS) is invariably used in all the present day geometric modeling packages. For an interactive modeling session, thousands of NURBS patches have to be computed and drawn per second. Such performance is beyond the reach of even the most advanced workstations available today. Advances in hardware support for parametric curve and patch generation have thus acquired increased importance. The authors give a complete hardware solution for the generation of NURBS patches.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 21 Sep 2007
Last Modified: 19 Sep 2010 04:38
URI: http://eprints.iisc.ac.in/id/eprint/11002

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