Srinivasan, MP and Muralidharan, MR and Nagabhushana, BS (1995) Design of a high speed communication controller for a multicomputer system-an FSM approach. In: 1st IWPP. Parallel Processing. Proceedings of the First International Workshop on Parallel Processing (IWPP-94), 26-31 Dec. 1994, Bangalore, India, pp. 418-423.
Full text not available from this repository. (Request a copy)Abstract
The paper describes the design of an interprocessor communication controller for a multicomputer system. The communication controller is designed using a finite state machine technique and implemented using off the shelf components. The communication controller operates with very little CPU intervention, hence the communication and computation can go in parallel. The communication controller interfaces the processing elements to a custom made bus with a FIFO memory for buffering the messages. It has built in intelligence to route the messages dynamically
| Item Type: | Conference Paper |
|---|---|
| Publisher: | Tata McGraw-Hill |
| Additional Information: | Copyright of this article belongs to Tata McGraw-Hill. |
| Keywords: | buffer storage;finite state machines;message passing;parallel architectures;parallel machines |
| Department/Centre: | Division of Electrical Sciences > Computer Science & Automation |
| Date Deposited: | 05 Sep 2007 |
| Last Modified: | 10 Jan 2012 07:27 |
| URI: | http://eprints.iisc.ac.in/id/eprint/10833 |
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