Browse by Author

Conference Proceedings

Kumar, Binod and Jindal, Ankit and Tudu, Jaynarayan and Pandey, Brajesh and Singh, Virendra (2017) Revisiting Random Access Scan for Effective hnhancement of Post-silicon Observability. In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), JUL 03-05, 2017, Thessaloniki, GREECE, pp. 132-137.

Ahlawat, Satyadev and Vaghani, Darshit and Tudu, Jaynarayan and Suhag, Ashok (2017) A Cost Effective Technique for Diagnosis of Scan Chain Faults. In: 21st International Symposium on VLSI Design and Test (VDAT), JUN 29-JUL 02, 2017, Indian Inst Technol Roorkee, Roorkee, INDIA, pp. 191-204.

Kumar, Binod and Nehru, Boda and Pandey, Brajesh and Singh, Virendra and Tudu, Jaynarayan (2017) A Technique for Low Power, Stuck-at Fault Diagnosable and Reconfigurable Scan Architecture. In: IEEE East-West Design and Test Symposium (EWDTS), OCT 14-17, 2016, Yerevan, ARMENIA.

Conference Paper

Tudu, Jaynarayan (2017) JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

Kumar, Binod and Nehru, Boda and Pandey, Brajesh and Tudu, Jaynarayan (2017) Skip-scan: A methodology for test time reduction. In: ter Science and Automation, Indian Institute of Science, Bangalore, India, 24-27 May 2016, Guwahati, India, pp. 1-6.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2016) A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test. In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), JUL 04-06, 2016, Catalunya, SPAIN, pp. 233-238.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2015) A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. In: 24th IEEE Asian Test Symposium, NOV 22-25, 2015, Mumbai, INDIA, pp. 25-30.

Subramanyan, Pramod and Jangir, Ram Rakesh and Tudu, Jaynarayan and Erik, Larsson and Singh, Virendra (2009) Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation. In: IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power during SoC Test. In: IEEE European Test Symposium (ETS) , May 2009.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Singh, Adit (2009) Capture Power Reduction for Modular System-on-Chip Test. In: 14th IEEE VLSI Design and Test Symposium (VDAT), Bangalore.