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Number of items: 30.

Kumar, Binod and Jindal, Ankit and Tudu, Jaynarayan and Pandey, Brajesh and Singh, Virendra (2017) Revisiting Random Access Scan for Effective hnhancement of Post-silicon Observability. In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), JUL 03-05, 2017, Thessaloniki, GREECE, pp. 132-137.

Kumar, Binod and Nehru, Boda and Pandey, Brajesh and Singh, Virendra and Tudu, Jaynarayan (2017) A Technique for Low Power, Stuck-at Fault Diagnosable and Reconfigurable Scan Architecture. In: IEEE East-West Design and Test Symposium (EWDTS), OCT 14-17, 2016, Yerevan, ARMENIA.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2016) A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test. In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), JUL 04-06, 2016, Catalunya, SPAIN, pp. 233-238.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2015) A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. In: 24th IEEE Asian Test Symposium, NOV 22-25, 2015, Mumbai, INDIA, pp. 25-30.

Siddhu, Lokesh and Mishra, Amit and Singh, Virendra (2014) Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design. In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 483-488.

Prasanth, V and Singh, Virendra and Parekhji, Rubin (2012) Derating Based Hardware Optimizations in Soft Error Tolerant Designs. In: 30th IEEE VLSI Test Symposium (VTS), APR 23-25, 2012, Hawaii, USA, pp. 282-287.

Kumar, Pawan and Singh, Virendra (2012) Efficient Regular Expression Pattern Matching for Network Intrusion Detection Systems using Modified Word-based Automata. In: 5th International Conference on Security of Information and Networks (SIN), OCT 25-27, 2012 , Malaviya Natl Inst Technol, Dept Comp Engn, Jaipur, INDIA, pp. 103-110.

Shayan, Md and Singh, Virendra and Singh, Adit D and Fujita, Masahiro (2012) SEU Tolerant Robust Memory Cell Design. In: IEEE 18th International On-Line Testing Symposium (IOLTS), JUN 27-29, 2012, Sitges, SPAIN, pp. 13-18.

Singh, Virendra and Fujita, Masahiro (2011) “Post silicon debug of SOC designs”. In: 2011 IEEE International SOC Conference (SOCC), 26-28 Sept. 2011, Taipei, p. 18.

Singh, Virendra and Karakoti, Ajay and Kumar, Amit and Saha, Abhishek and Basu, Saptarshi and Seal, Sudipta (2010) Precursor Dependent Microstructure Evolution and Nonstoichiometry in Nanostructured Cerium Oxide Coatings Using the Solution Precursor Plasma Spray Technique. In: Journal of the American Ceramic Society, 93 (11). pp. 3700-3708.

Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding. In: IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), JUN 28-JUL 01, 2010, Chicago, IL,, pp. 121-130.

Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-efficient redundant execution for chip multiprocessors. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI (GLSVLSI '10), May 16-18, 2010, Brown University Campus, Providence, Rhode Island, USA.

Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K and Fujiwara, Hideo and Singh, Adit D (2010) On Minimization of Test Application Time for RAS. In: 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems, JAN 03-07, 2010, Bangalore, India, pp. 393-398.

Abhishek, A and Khan, Amanulla and Singh, Virendra and Saluja, Kewal K and Singh, Adit D (2010) Test Application Time Minimization for RAS using Basis Optimization of Column Decoder. In: International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), MAY 30-JUN 02, 2010, Paris, FRANCE, pp. 2614-2617.

Choudhary, Naveen and Gaur, MS and Laxmi, Vijay and Singh, Virendra (2009) Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip. In: IEEE INDICON 2009, 18-20 Dec. 2009, Gujarat.

Choudhary, Naveen and Gaur, MS and Laxmi, Vijay and Singh, Virendra (2009) Designing Application Specific Irregular Topology for Network-on-Chip. In: 17th International Conference on Advanced Computing and Communications (ADCOM) 2009, Dec 2009.

Rajesh, Venkat and Erik, Larsson and Gaur, MS and Singh, Virendra (2009) A Odd-Even DFD for scan chain diagnosis. In: 10th IEEE Workshop on RTL and High Level Test (WRTLT), Nov 2009, Hong Kong.

Subramanyan, Pramod and Jangir, Ram Rakesh and Tudu, Jaynarayan and Erik, Larsson and Singh, Virendra (2009) Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation. In: IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia.

Sindia, Suraj and Singh, Virendra and Agrawal , Vishwani (2009) V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits. In: IEEE East West Design and Test Symposium (EWDTS) 2009, Sep 2009, Moscow, Russia.

Sindia, Suraj and Singh, Virendra and Agrawal, Vishwani (2009) Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing. In: 14th IEEE VLSI Design and Test Symposium (VDAT), July 2009, Bangalore.

Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K (2009) Power Efficient Redundant Execution for Chip Multiprocessor. In: Workshop on Dependable and Secure Nanocomputing (WDSN) 2009, June 2009, Lisbon, Portugal.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power during SoC Test. In: IEEE European Test Symposium (ETS) , May 2009.

Sindia, Suraj and Singh, Virendra and Agrawal, Vishwani D (2009) Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits. In: 18th IEEE North Atlantic Test Workshop (NATW) , May 2009, Boxborough, MA, USA.

Vayrynen, Mikael and Singh, Virendra and Larsson, Erik (2009) Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on Chips. In: International Conference on Design Automation and Test in Europe (DATE), Nice, 20-24 April 2009 , Nice.

Vinay, NS and Larsson, Erik and Singh, Virendra (2009) Thermal Aware Test Methodology of 3-D Integrated SoC. In: Workshop on 3-D Integration: Architecture, Design and Test (in conjunction with DATE’09), Apr 2009.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Singh, Adit (2009) Capture Power Reduction for Modular System-on-Chip Test. In: 14th IEEE VLSI Design and Test Symposium (VDAT), Bangalore.

Deepak, KG and Reyna, Robinson and Singh, Virendra and Singh, Adit D (2009) Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.

Sindia, Suraj and Singh, Virendra and Agrawal, Vishwani D (2009) Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.

Tudu, Jaynarayan T and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power for Scan Circuit during Test. In: 14th IEEE European Test Symposium (EST 2009), May 25-29, 2009, Seville, SPAIN, pp. 25-30.

Singh, Virendra and Larsson, Erik (2008) On Reduction of Capture Powerfor Modular System-on-Chip Test. In: IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, JAPAN, November 27-28, 2008, November 27-28, 2008, Sapporo.

This list was generated on Thu Dec 3 16:26:18 2020 IST.