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Sathe, Chaitanya and Dan, Surya Shankar and Mahapatra, Santanu (2008) Assessment of SET Logic Robustness Through Noise Margin Modeling. In: IEEE Transactions on Electron Devices, 55 (3). pp. 909-915.
Sathe, Chaitanya and Mahapatra, Santanu (2007) Modeling and Analysis of Noise Margin in SET Logic. In: 20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, JAN 06-10, 2007, Bangalore.