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Conference Paper

Ramanathan, S and Gautam, G and Srinivasan, V and Parag, P (2022) Latency-Redundancy Tradeoff in Distributed Read-Write Systems. In: 14th International Conference on COMmunication Systems and NETworkS, 4-8 Jan 2022, Bangalore, pp. 172-180.

Nandy, SK and Ramanathan, S and Visvanathan, V (2002) Synthesis of configurable architectures for DSP algorithms. In: 12th International Conference on VLSI Design, 7-10 Jan 1999, Goa , India.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of Congurable Architectures for DSP Algorithms. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa,India, pp. 350-357.

Ramanathan, S and Visvanathan, V (1997) Low-Power Configurable Processor Array for DLMS Adaptive Filtering. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 198 -203.

Ramanathan, S and Visvanathan, V (1996) A Systolic Architecture for LMS Adaptive Filtering with Minimal Adaptation Delay. In: Ninth International Conference on VLSI Design, 1996, 3-6 January, Bangalore,India, pp. 286-289.

Visvanathan, V and Ramanathan, S (1994) Synthesis of energy-efficient configurable processor arrays. In: First International Workshop on Parallel Processing:IWPP'94, 26-31 December 1994, Bangalore, India, pp. 627-632.

Visvanathan, V and Mohanty, Nibedita and Ramanathan, S (1993) An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. In: Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 166-171.

Ramanathan, S and Mohanty, Nibedita and Visvanatha, V (1993) A Methodology for Generating Application Specific Tree Multipliers. In: Sixth International Conference on VLSI Design, 1993, 3-6 January, Bombay,India, 176 -179.

Journal Article

Ramanathan, S and Nandy, SK and Visvanathan, V (2000) Reconfigurable Filter Coprocessor Architecture for DSP Applications. In: The Journal of VLSI Signal Processing, 26 (3). pp. 333-359.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) A computational engine for multirate FIR digital filtering. In: Signal Processing, 79 (2). pp. 213-222.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. In: Journal of VLSI Signal Processing, 22 (3). pp. 173-195.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of ASIPs for DSP algorithms. In: Integration, the VLSI Journal, 28 (1). 13-32 .

Ramanathan, S and Visvanathan, V (1999) Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay. In: Integration, the VLSI Journal, 27 (1). pp. 1-32.

Kishore, * and Ramanathan, S and Rao, RMVGK (1996) Repeated drop weight impacts and post-impact ILSS tests on glass-epoxy composite. In: Bulletin of Materials Science, 19 (6). pp. 1133-1141.