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Mahapatra, Ipsita Biswas and Nandy, SK (2018) An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification. In: 2018 IEEE International Reliability Physics Symposium, IRPS 2018; Burlingame; United States; 11 March, 11-15 March 2018, Burlingame, CA, USA, pp. 85-89.
Mahapatra, Ipsita Biswas and Agarwal, Utkarsh and Nandy, SK (2018) DFG partitioning algorithms for coarse grained reconfigurable array assisted RTL simulation accelerators. In: IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), MAR 16-17, 2018, Bangalore, INDIA. (In Press)
Natarajan, Santhi and KrishnaKumar, N and Pavan, M and Pal, Debnath and Nandy, SK (2018) ReneGENE-DP: Accelerated Parallel Dynamic Programming for Genome Informatics. In: IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), MAR 16-17, 2018, Bangalore, INDIA.
Merchant, Farhad and Vatwani, Tarun and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2016) Achieving Efficient QR Factorization by Algorithm-Architecture Co-Design of Householder Transformation. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 98-103.
Merchant, Farhad and Choudhary, Nimash and Nandy, SK and Narayan, Ranjani (2016) Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 415-420.
Madhu, Kavitha T and Das, Saptarsi and Nalesh, S and Nandy, SK and Narayan, Ranjani (2015) Compiling HPC Kernels for the REDEFINE CGRA. In: 2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC), AUG 24-26, 2016, Int Symposium Cyberspace Safety & Secur, New York, NY, pp. 405-410.
Nalesh, S and Madhu, Kavitha T and Das, Saptarsi and Nandy, SK and Narayan, Ranjani (2015) Energy Aware Synthesis of Application Kernels expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. In: IEEE International Symposium on Nanoelectronic and Information Systems, DEC 21-23, 2015, Indore, INDIA, pp. 7-12.
Kachore, Vaibhav Ankush and Lakshmi, J and Nandy, SK (2015) LOCATION OBFUSCATION FOR LOCATION DATA PRIVACY. In: IEEE 11th World Congress on Services, JUN 27-JUL 02, 2015, New York, NY, pp. 213-220.
Biswas, Arnab Kumar and Nandy, SK and Narayan, Ranjani (2015) Network-on-Chip Router attacks and their prevention in MP-SoCs with multiple Trusted Execution Environments. In: IEEE International Conference on Electronics Computing and Communication Technologies (CONECCT), JUL 10-11, 2015, Bangalore, INDIA.
Mahapatra, Ipsita Biswas and Natarajan, Santhi and Nalesh, S and Nandy, SK (2015) SIMAAH: RTL simulation accelerator for complex SoC's. In: IEEE International Conference on Electronics Computing and Communication Technologies (CONECCT), JUL 10-11, 2015, JUL 10-11, 2015.
Mahadurkar, Mahesh and Merchant, Farhad and Maity, Arka and Vatwani, Kapil and Munje, Ishan and Gopalan, Nandhini and Nandy, SK and Narayan, Ranjani (2014) Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 225-232.
Merchant, Farhad and Chattopadhyay, Anupam and Garga, Ganesh and Nandy, SK and Narayan, Ranjani and Gopalan, Nandhini (2014) Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 258-263.
Madhu, Kavitha T and Das, Saptarsi and Krishna, Madhava C and Nalesh, S and Nandy, SK and Narayan, Ranjani (2014) Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 215-224.
Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.
Dhingra, Mohit and Lakshmi, J and Nandy, SK and Bhattacharyya, Chiranjib and Gopinath, K (2013) Elastic Resources Framework in IaaS, preserving performance SLAs. In: IEEE 6th International Conference on Cloud Computing (CLOUD), JUN 27-JUL 03, 2013, Santa Clara, CA, pp. 430-437.
Kala, S and Nalesh, S and Maity, Arka and Nandy, SK and Narayan, Ranjani (2013) High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-23, 2013, Beijing, PEOPLES R CHINA, pp. 3034-3037.
Anand, Ankit and Dhingra, Mohit and Lakshmi, J and Nandy, SK (2012) Resource usage monitoring for KVM based virtual machines. In: 18th Annual International Conference on Advanced Computing and Communications (ADCOM), DEC 14-16, 2012 , Bangalore, INDIA , pp. 66-70.
Rao, Adarsha and Nandy, SK and Deprettere, Ed F and Nikolov, Hristo (2011) USHA: unified software and hardware architecture for video decoding. In: 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 5-6 June 2011, San Diego, CA, USA.
Das, Saptarsi and Varadarajan, Keshavan and Garga, Ganesh and Mondal, Rajdeep and Narayan, Ranjani and Nandy, SK (2011) A method for flexible reduction over binary fields using a field multiplier. In: SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, 18-21 July, Seville, Spain.
Surendra, G and Banerjee, Subhasis and Nandy, SK (2003) Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. In: Design, Automation And Test in Europe Conference And Exhibition,Proceedings, MAR 03-07, 2003, Munich, Germany.
Kulkarni, V and Emelyanov, P and Ponomaryov, D and Krishna, M and Raha, S and Nandy, SK (2019) Parallel Factorization of Boolean Polynomials. In: 12th International Andrei P. Ershov Informatics Conference, PSI 2019; Novosibirsk; Russian Federation, 2-5 July 2019, Novosibirsk; Russian Federation, pp. 80-94.
Singh, R and Ranga, SV and Patil, S and Krishna, M and Mehta, M and Anoop, MN and Nandy, SK and Haldar, C and Narayan, R and Neumann, F and Baufreton, P (2019) Micro-Architectural support for High Availability of NoC-based MP-SoC. In: 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC), 8-12 Sept. 2019, San Diego, CA, USA, USA.
Khamvilai, T and Sutter, L and Mains, JB and Feron, E and Baufreton, P and Neumann, F and Krishna, M and Nandy, SK and Narayan, R and Haldar, C (2019) Task Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architectures with an Application on Control of Propulsion System. In: 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC), 8-12 Sept. 2019, San Diego, CA, USA, USA.
Merchant, F and Vatwani, T and Chattopadhyay, A and Raha, S and Nandy, SK and Narayan, R and Leupers, R (2019) Applying modified householder transform to Kalman filter. In: 32nd International Conference on VLSI Design,, 5 January 2019 - 9 January 2019, New Delhi, pp. 431-436.
Merchant, F and Vatwani, T and Chattopadhyay, A and Raha, S and Nandy, SK and Narayan, R and Leupers, R (2019) A systematic approach for acceleration of matrix-vector operations in cgra through algorithm-architecture co-design. In: 32nd International Conference on VLSI Design, VLSID 2019, 5 January 2019 - 9 January 2019, New Delhi, pp. 64-69.
Sutter, Louis and Khamvilai, Thanakorn and Monmousseau, Philippe and Mains, John B and Feron, Eric and Baufreton, Philippe and Neumann, Francois and Krishna, Madhava and Nandy, SK and Narayan, Ranjani and Haldar, Chandan (2018) Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture. In: IEEE/AIAA 37th Digital Avionics Systems Conference (DASC), SEP 23-27, 2018, London, ENGLAND, pp. 833-842.
Natarajan, S and KrishnaKumar, N and Anuchan, HV and Pal, D and Nandy, SK (2018) ReneGENE-Novo: Co-designed algorithm-architecture for accelerated preprocessing and assembly of genomic short reads. In: 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, 2 - 4 May 2018, Santorini, pp. 564-577.
Merchant, F and Vatwani, T and Chattopadhyay, A and Raha, S and Nandy, SK and Narayan, R (2018) Achieving efficient realization of kalman filter on CGRA through algorithm-architecture co-design. In: 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, 2 - 4 May 2018, Santorini, pp. 119-131.
Natarajan, S and KrishnaKumar, N and Pal, D and Nandy, SK (2018) ReneGENE-GI: Empowering precision genomics with FPGAs on HPCs. In: 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, 2 - 4 May 2018, Santorini, pp. 178-191.
Mahapatra, IB and Agarwal, U and Azad, C and Nandy, SK (2018) Design Space Exploration of an Execution-Driven Functional Simulation Methodology. In: 31st International Conference on VLSI Design, VLSID 2018, 6 - 10 January 2018, Pune, pp. 295-300.
Guillaumet, Tom and Feron, Eric and Baufreton, Philippe and Neumann, Francois and Madhu, Kavitha and Krishna, Madhava and Nandy, SK and Narayan, Ranjani and Haldar, Chandan (2017) Task Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architectures. In: 2017 IEEE/AIAA 36TH DIGITAL AVIONICS SYSTEMS CONFERENCE (DASC) , SEP 17-21, 2017, St Petersburg, FL.
Mohammadi, Mahnaz and Satpute, Nitin and Ronge, Rohit and Chandiramani, Jayesh Ramesh and Nandy, SK and Raihan, Aamir and Verma, Tanmay and Narayan, Ranjani and Bhattacharya, Sukumar (2015) A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 505-510.
Mahale, Gopinath and Mahale, Hamsika and Goel, Arnav and Nandy, SK and Bhattacharya, S and Narayan, Ranjani (2015) Hardware Solution For Real-time Face Recognition. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 81-86.
Merchant, Farhad and Maity, Arka and Mahadurkar, Mahesh and Vatwani, Kapil and Munje, Ishan and Krishna, Madhava and Nalesh, S and Gopalan, Nandhini and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2015) Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 153-158.
Dhingra, Mohit and Lakshmi, J and Nandy, SK (2012) Resource Usage Monitoring in Clouds. In: ACM/IEEE 13th International Conference on Grid Computing, 20-23 September 2012, Beijing, China.
Krishnamoorthy, Ratna and Varadarajan, Keshavan and Fujita, Masahiro and Nandy, SK (2011) Spatio-temporal computation on a coarse grained reconfigurable architecture. In: 7th International Symposium on Applied Reconfigurable Computing, 23-25 March 2011, Belfast, United Kingdom.
Biswas, Prasenjit and Alle, Mythri and Nandy, SK and Narayan, R and Varadarajan, Keshavan (2010) Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. In: 2010 International Conference on Embedded Computer Systems (SAMOS), 19-22 July 2010, Samos.
Biswas, P and Narayan, R and Nandy, SK and Alle, Mythri and Varadarajan, K and Mondal, R and Udupa, PP (2010) Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. In: 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 5-7 July 2010, Lixouri, Kefalonia.
Alle, Mythri and Varadarajan, Keshavan and Fell, Alexander and Nandy, SK (2009) Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. In: 5th International Workshop on Applied Reconfigurable Computing, Mar 16-18, 2009, Karlsruhe, Germany.
Rajore, Ritesh and Nandy, SK and Jamadagni, HS (2009) Architecture of Run-time Reconfigurable Channel Decoder. In: IEEE International Conference on Communications (ICC 2009), JUN 14-18, 2009, Dresden, pp. 2961-2966.
Fell, Alexander and Biswas, Prasenjit and Chetia, Jugantor and Nandy, SK and Narayan, Ranjani (2009) Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT. In: IEEE International SOC Conference, SEP 09-11, 2009, Belfast, pp. 251-254.
Garga, Ganesh and Guevorkian, David and Nandy, SK and Jamadagni, HS (2009) High-Throughput Flexible Constraint Length Viterbi Decoders on De Bruijn, Shuffle-Exchange and Butterfly Connected Architectures. In: International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation, JUL 20-23, 2009, Samos, pp. 157-164.
Rao, Adarsha and Alle, Mythri and Sainath, V and Shaik, Reyaz and Chowhan, Rajashekhar and Sankaraiah, S and Mantha, Sravanthi and Nandy, SK and Narayan, Ranjani (2009) An Input Triggered Polymorphic ASIC for H.264 Decoding. In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 07-09, 2009, Boston, MA, USA, pp. 106-113.
Lakshmi, J and Nandy, SK (2009) Modeling Architecture-OS interactions using Layered Queuing Network Models. In: International Conference Proceedings of the HPC-Asia 2009 .
Satrawala, AN and Nandy, SK (2009) RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture. In: Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. International Symposium on, JUL 20-23, 2009, Samos, pp. 82-91.
Fell, Alexander and Alle, Mythri and Varadarajan, Keshavan and Biswas, Prasenjit and Das, Saptarsi and Chetia, Jugantor and Nandy, SK and Narayan, Ranjani (2009) Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration. In: proceedings of the 2009 International Conference on Compilers,Architecture and Synthesis for Embedded Systems (CASES 2009),, Grenoble,Frane.
Garga, Ganesh and Alle, Mythri and Varadarajan, Keshavan and Nandy, SK and Jamadagni, HS (2008) Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. In: 10th International Symposium on System-on-chip, Nov 4-6, 2008, held in Tampere, Finland, 5-6 Nov. 2008 , Tampere.
Rao, Adrsha and Mythri, * and Nandy, SK and Narayan, Ranjani (2008) Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven.
Nimmy, J and Reddy, C Ramesh and Varadarajan, K and Alle, M and Fell, A and Nandy, SK and Narayan, R (2008) RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven.
Rajore, Ritesh and Garga, Ganesh and Jamadagni, HS and Nandy, SK (2008) Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven.
Satrawala, AN and Varadarajan, Keshavan and Alle, Mythri and Nandy, SK and Narayan, Ranjani (2007) REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. In: Proceedings of the International Conference on Field Programmable Logic and Applications, FPL 2007, Amsterdam, Aug 2007., 27-29 Aug. 2007 , Amsterdam .
Alle, Mythri and Biswas, J and Nandy, SK (2007) High performance VLSI implementation for H.264 Inter/Intra prediction. In: International Conference on Consumer Electronics:ICCE 2007, Digest of Technical Papers, 10-14 January 2007, Las Vegas, NV, pp. 1-2.
Biswas, Jayanta and Nandy, SK (2006) Efficient Key Management and Distribution for MANET. In: IEEE International Conference on Communications, 2006. ICC '06, June 2006, Istanbul.
Kalapriya, K and Nandy, SK (2006) On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. In: International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies 2006. ICN/ICONS/MCL 2006. , 23-29 April 2006.
Lakshmi, J and Nandy, SK and Narayan, Ranjani and Varadarajan, Keshavan (2006) Framework for enabling highly available distributed applications for utility computing. In: 4th International Symposium on Parallel and Distributed Processing and Applications,, Dec 04-06, 2006, Sorrento, Italy, pp. 549-560.
Alle, Mythri and Biswas, J and Nandy, SK (2006) High performance VLSI architecture design for H.264 CAVLC decoder. In: 17th IEEE International Conference on Application-Specific Systems ArchiteSteamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 317-322.
Varadarajan, Keshavan and Nandy, SK and Sharda, Vishal and Bharadwaj, Amrutur and Iyer, Ravi and Makineni, Srihari and Newell, Donald (2006) Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. In: 39th Annual IEEE/ACM International Symposium on Microarchitecture,, Dec 09-13, 2006, Orlando, FL, pp. 433-442.
Alle, Mythri and Nandy, SK and Biswas, J (2006) Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer. In: In Proceedings of Distributed Multimedia Systems 2006, August 30-September 1, Grand Canyon, USA.
Singh, Sandeep B and Biswas, Jayanta and Nandy, SK (2006) A cost effective pipelined divider for double precision floating point number. In: 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Steamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 132-137.
Bharath, N and Nandy, SK and Nagaraju, Bussa (2005) Artificial deadlock detection in process networks for ECLIPSE. In: IEEE 16th International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2005, 23-25 July 2005, Samos, Greece, pp. 22-27.
Nainwal, KC and Lakshmi, J and Nandy, SK and Narayan, Ranjani and Varadarajan, K (2005) A Framework for QoS Adaptive Grid Meta Scheduling. In: Sixteenth International Workshop on : Database and Expert Systems Applications, 2005, 22-26 August, Denmark, pp. 292-296.
Biswas, Jayanta and Nandy, SK (2005) Quality of support for multicasting over mobile ad-hoc networks. In: International Conference on Wireless Networks, Communications and Mobile Computing, JUN 13-16, 2005, Maui, HI.
Kalapriya, K and Nandy, SK (2005) Throughput Driven, Highly Available Streaming Stored Playback Video Service Over a Peer-to-Peer Network. In: 19th International Conference on Advanced Information Networking and Applications, 2005. AINA 2005, 28-30 March, Taiwan, Vol.2, 229 -234.
Biswas, Jayanta and Nandy, SK (2004) Application Layer Multicasting for Mobile Ad-Hoc Networks with Network Layer Support. In: 29th Annual IEEE International Conference on Local Computer Networks, 2004, 16-18 November, Florida,USA, 24 -31.
Kalapriya, K and Nandy, SK and Satish, V and Maheshwari, Uma R and Srinivas, Deepti (2004) An Architectural View of the Entities Required for Execution of Task in Pervasive Space. In: 10th IEEE International Workshop on Future Trends of Distributed Computing Systems. FTDCS 2004, 26-28 May, Suzhou,China, 37 -43.
Kalapriya, K and Nandy, SK and Babu, Venkatesh K (2004) Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure ? In: 18th International Conference on Advanced Information Networking and Application (AINA’04), 29-31 March 2004, Fukuoka City, Japan., vol 2, 200-203.
Biswas, Jayanta and Barai, Mukti and Nandy, SK (2004) Efficient Hybrid Multicast Routing Protocol for Ad-Hoc Wireless Networks. In: 29th Annual IEEE International Conference on Local Computer Networks, 2004, 16-18November, Florida,USA, pp. 180-187.
Banerjee, Subhasis and Surendra, G and Nandy, SK (2004) Exploiting Program Execution Phases to Trade Power and Performance for Media Workload. In: the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, 2004, 27-30 January, Yokohama,Japan, pp. 387-389.
Surendra, G and Banerjee, Subhasis and Nandy, SK (2004) Exploiting the Behavior of Ready Instructions for Power Benefits in a Dynamically Scheduled Embedded Processor. In: The 2004 47th Midwest Symposium on Circuits and Systems, MWSCAS '04, 25-28 July, Hiroshima,Japan, Vol.2, 441 -444.
Banerjee, Subhasis and Surendra, G and Nandy, SK (2004) On the Effectiveness of Dynamically Allocating Resources Across Program Execution Phases for Media Workloads. In: The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004, 6-9 December, Tainan,Taiwan, Vol.1, 9-12.
Surendra, G and Banerjee, Subhasis and Nandy, SK (2004) Power-Performance Trade-off using Pipeline Delays. In: the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, 2004, 27-30 January, Yokohama,Japan, pp. 384-386.
Bharath, N and Nandy, SK (2004) A Runtime Mechanism for Detection of Artificial Deadlocks in Process Networks. In: The 2004 47th Midwest Symposium on Circuits and Systems. MWSCAS '04, 25-28 July, Hiroshima,Japan, Vol.2, 437-440.
Kalapriya, K and Babu, Venkatesh R and Nandy, SK (2004) Streaming Stored Playback Video Over a Peer-to-Peer Network. In: 2004 IEEE International Conference on Communications, 20-24 June, Paris, Vol.3, 1298 -1302.
Kalapriya, K and Nandy, SK and Srinivasan, Deepti and Maheshwari, Uma R and Satish, V (2004) A framework for resource discovery in pervasive computing for mobile aware task execution. In: Proceedings of the 1st Conference on Computing frontiers, 14–16, April 2004, Ischia, Italy., pp. 70-77.
Kalapriya, K and Raghucharan, BR and Lele, Abhijit M and Nandy, SK (2003) Dynamic Traffic Profiling for Efficient Link Bandwidth Utilization in QoS Routing. In: The 9th Asia-Pacific Conference on Communications, 2003. APCC 2003, 21-24 September, Penang,Malaysia, Vol.2, 486-493.
Rao, Pradeep H and Nandy, SK (2003) Evaluating Compiler Support for Complexity Effective Network Processing. In: Workshop on Complexity-Effective Design held in conjunction with the 30th International Symposium on Computer Architecture (ISCA), June 2003, San Diego, California. USA..
Menon, Amitabh and Nandy, SK and Mehendale, Mahesh (2003) Multivoltage Scheduling with Voltage-Partitioned Variable Storage. In: 2003 International Symposium on Low Power Electronics and Design, August 25 - 27, 2003, Seoul, Korea, pp. 298-301.
Kalapriya, K and Raghucharan, BR and Lele, AM and Nandy, SK (2003) Traffic Profiling for Efficient Network Resource Utilization. In: 4th International Conference on Internet Computing (IC 03), JUN 23-26, 2003, Las Vegas, Nevada.
Kiran, Satya MNV and Jayram, MN and Rao, Pradeep and Nandy, SK (2003) A complexity effective communication model for behavioral modeling of signal processing applications. In: Annual ACM IEEE Design Automation Conference, June 02 - 06, 2003, Anaheim, CA, USA, pp. 412-415.
Nandy, SK and Ramanathan, S and Visvanathan, V (2002) Synthesis of configurable architectures for DSP algorithms. In: 12th International Conference on VLSI Design, 7-10 Jan 1999, Goa , India.
Agarwal, Manvi and Nandy, SK and Eijndhoven, JV and Balakrishanan, S (2002) Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors. In: 15th Symposium on Integrated Circuits and Systems Design, 9-14 September, Porto Alegre,Brazil, pp. 43-48.
Agarwal, Manvi and Nandy, SK (2002) Speculative Trace Scheduling in VLIW Processors. In: 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'2002, 16-18 September, Freiburg,Germany, pp. 408-413.
Lele, Abhijit M and Nandy, SK (2001) Architecture of Reconligurable a Low Power Gigabit ATM Switch. In: Fourteenth International Conference on VLSI Design, 2001, 3-7 January, Bangalore,India, 242 -247.
Ahmed, Arshad and Nandy, SK and Sathya, Paul (2001) Content Adaptive Motion Estimation for Mobile Video Encoders. In: The 2001 IEEE International Symposium on Circuits and Systems. ISCAS 2001, 6-9 May, Sydney,Australia, Vol.2, 237 -240.
Surendra, G and Nandy, SK and Paul, Paul (2001) ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. In: Fourteenth International Conference on VLSI Design, 2001, 3-7 January, Bangalore,India, 85 -90.
Rao, Srikanth M and Nandy, SK (2000) Controller Redesign Based Clock and Register Power Minimization. In: 2000 IEEE International Symposium on Circuits and Systems. ISCAS 2000, 28-31 May, Geneva,Switzerland, Vol.3, 275-278.
Lele, AM and Nandy, SK and Epema, DHJ (2000) Design Space Exploration for Providing QoS Within the Harmony Framework. In: 2000 IEEE International Conference on Multimedia and Expo. ICME 2000, 30 July-2 August, New York,USA, Vol.1, 521 -524.
Balakrishnan, S and Nandy, SK (2000) Performance Evaluation of Multithreaded Architectures for Media Processing Applications. In: 2000 IEEE International Symposium on Circuits and Systems. ISCAS 2000, 28-31 May, Geneva,Switzerland, Vol.1, 531-534.
Rao, Srikanth M and Nandy, SK (2000) Power minimization using control generated clocks. In: 37th Design Automation Conference, 5-9 June, 2000, Los Angeles, USA, 794 -799.
Lele, A and Nandy, SK (1999) Harmony-a framework for providing quality of service in wireless mobile computing environment. In: Proceedings of 6th International Conference on High Performance Computing (HiPC'99) - Mobile Computing for this Millenium, 17-20 Dec. 1999, Calcutta, India, pp. 299-308.
Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of Congurable Architectures for DSP Algorithms. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa,India, pp. 350-357.
Balakrishnan, S and Nandy, SK (1998) Arbitrary Precision Arithmetic - SIMD Style. In: 1998 Eleventh International Conference on VLSI Design, 4-7 January, Chennai,India, pp. 128-132.
Lele, Abhijit and Nandy, SK (1998) Can QOS Guarantees be Supported for Live Video Over ATM Networks? In: IEEE Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration, 8-12 November, Sydney, Vol.2, 1264 -1272.
Balakrishnan, S and Nandy, SK and van Gemund, Arjan JC (1997) Modeling Multi-threaded Architectures in PAMELA for Real-time High Performance Applications. In: Fourth International Conference on High Performance Computing, 1997, 18-21 December, Bangalore,India, 407 -414.
Giri, A and Visvanathan, V and Nandy, SK and Ghoshal, SK (1994) High Speed Digital Filtering on SRAM-based FPGAs. In: Seventh International Conference on VLSI Design, 1994, 5-8 January, Kolkotta,India, 229 -232.
Rathna, GN and Nandy, SK and Parthasarathy, K (1994) A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. In: Seventh International Conference on VLSI Design, 1994, 5-8 January, Kolkata, pp. 225-228.
Ghosh, Debabrata and Nandy, SK and Parthasarathy, K and Visvanathan, V (1993) NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. In: The Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 341-346.
Nandy, SK and Narayanan, R and Visvanathan, V and Sadayappan, P and Chauhan, PS (1993) A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. In: 1993 International Conference on Parallel Processing, AUG 16-20, 1993, SYRACUSE UNIV, SYRACUSE, NY,.
Prakash, CE and Nandy, SK (1990) VOXEL Based Modeling and Rendering Irregular Solids. In: of the Sixteenth EUROMICRO Symposium on Microprocessing and Microprogramming (EUROMICRO 90), 27-30 Aug. 1990, Amsterdam, Netherlands, pp. 341-346.
Bhat, NB and Nandy, SK (1989) Special Purpose Architecture for Accelerating Bitmap DRC. In: 26th Conference on Design Automation, 1989, 25-29 June, Las Vegas,Nevada,USA, 674 -677.
Ferraz, O and Subramaniyan, S and Chinthalaa, R and Andrade, J and Cavallaro, JR and Nandy, SK and Silva, V and Zhang, X and Purnaprajna, M and Falcao, G (2022) A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. In: IEEE Communications Surveys and Tutorials, 24 (1). pp. 524-556.
Emelyanov, PG and Krishna, M and Kulkarni, V and Nandy, SK and Ponomaryov, DK and Raha, S (2021) Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation. In: Programming and Computer Software, 47 (2). pp. 108-118.
Natarajan, S and Krishna Kumar, N and Pal, D and Nandy, SK (2020) Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective. In: Journal of Signal Processing Systems, 92 (10). pp. 1197-1213.
Mahapatra, IB and Nandy, SK (2019) Ex-Drive: An execution driven functional verification flow. In: Journal of Low Power Electronics, 15 (2). pp. 168-181.
Merchant, Farhad and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2017) Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. In: Parallel Processing Letters, 27 (3-4). ISSN 0129-6264
Mahale, Gopinath and Mahale, Hamsika and Nandy, SK and Narayan, Ranjani (2016) REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 27 (12). pp. 3602-3616.
Biswas, Arnab Kumar and Nandy, SK (2016) Role based shared memory access control mechanisms in NoC based MP-SoC. In: NANO COMMUNICATION NETWORKS, 7 . pp. 46-64.
Biswas, Arnab Kumar and Nandy, SK and Narayan, Ranjani (2015) Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. In: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 34 (10). pp. 3241-3290.
Das, Saptarsi and Madhu, Kavitha and Krishna, Madhav and Sivanandan, Nalesh and Merchant, Farhad and Natarajan, Santhi and Biswas, Ipsita and Pulli, Adithya and Nandy, SK and Narayan, Ranjani (2014) A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. In: JOURNAL OF SYSTEMS ARCHITECTURE, 60 (7). pp. 592-614.
Garga, Ganesh and Das, Saptarsi and Nandy, SK and Narayan, Ranjani and Haldar, Chandan and Jagtap, Maheshkumar P and Dash, Siba Prasad (2012) A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture. In: Defence Science Journal, 62 (1). pp. 25-31.
Alle, Mythri and Varadarajan, Keshavan and Fell, Alexander and Reddy, Ramesh C and Joseph, Nimmy and Das, Saptarsi and Biswas, Prasenjit and Chetia, Jugantor and Rao, Adarsh and Nandy, SK and Narayan, Ranjani (2009) Redefine: Runtime Reconfigurable Polymorphic ASIC. In: ACM Transactions in Embedded Computing Systems (TECS), 9 (2).
Lakshmi, J and Nandy, SK (2009) I/O Device Virtualization in the multi-core era, a QoS perspective. In: Grid and Pervasive Computing Conference, 2009. GPC '09 . pp. 128-135.
Banerjee, Subhasis and Surendra, G and Nandy, SK (2008) On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. In: Journal of Systems Architecture, 54 (8). pp. 797-815.
Sarojadevi, H and Nandy, SK and Balakrishnan, S (2004) On the Correctness of Program Execution when Cache Coherence is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. In: International Journal of Parallel Programming, 32 (5). pp. 415-446.
Surendra, G and Banerjee, S and Nandy, SK (2003) On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. In: International Journal of Parallel Programming, 31 (6). pp. 469-487.
Ramanathan, S and Nandy, SK and Visvanathan, V (2000) Reconfigurable Filter Coprocessor Architecture for DSP Applications. In: The Journal of VLSI Signal Processing, 26 (3). pp. 333-359.
Lele, AM and Nandy, SK and Epema, DHJ (2000) Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. In: Journal of Interconnection Networks, 1 (3). pp. 247-266.
Ramanathan, S and Visvanathan, V and Nandy, SK (1999) A computational engine for multirate FIR digital filtering. In: Signal Processing, 79 (2). pp. 213-222.
Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. In: Journal of VLSI Signal Processing, 22 (3). pp. 173-195.
Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of ASIPs for DSP algorithms. In: Integration, the VLSI Journal, 28 (1). 13-32 .
Menezes, Vinod and Nandy, SK and Mitra, Biswadip (1997) Signal compression through spatial frequency-based motion estimation. In: Integration, the VLSI Journal, 22 (1-2). pp. 115-135.
Ghosh, D and Nandy, SK (1995) Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. In: IEEE Transactions on Very Large Scale Integration Systems, 3 (1). pp. 36-48.
Balakrishnan, S and Nandy, SK (1990) Quasi Dynamic Approach to Layout Compaction. In: Microprocessing and Microprogramming, 30 (1-5). pp. 231-236.
Nandy, SK and Deogaonkar, Anuradha and Moona, Rajat and Madhuri, Sudha C (1990) K-d tree based gridless maze routing on message passing multiprocessor systems. In: Journal of the Institution of Electronics and Telecommunication Engineers, 36 (4). pp. 287-293.
Nandy, SK and Patnaik, LM (1987) Algorithm for incremental compaction of geometrical layouts. In: Computer-Aided Design, 19 (2). pp. 257-265.
Nandy, SK and Patnaik, LM (1986) Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts. In: Computer-Aided Design, 18 (7). 380 -388.
Rao, Pradeep H and Nandy, SK and Kiran, Satya MNV (2003) Simultaneous MultiStreaming for complexity-effective VLIW architectures. In: Lecture Notes in Computer Science, 2823 . pp. 166-179.
