|
 | Up a level |
Merchant, Farhad and Vatwani, Tarun and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2016) Achieving Efficient QR Factorization by Algorithm-Architecture Co-Design of Householder Transformation. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 98-103.
Merchant, Farhad and Choudhary, Nimash and Nandy, SK and Narayan, Ranjani (2016) Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 415-420.
Mahadurkar, Mahesh and Merchant, Farhad and Maity, Arka and Vatwani, Kapil and Munje, Ishan and Gopalan, Nandhini and Nandy, SK and Narayan, Ranjani (2014) Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 225-232.
Merchant, Farhad and Chattopadhyay, Anupam and Garga, Ganesh and Nandy, SK and Narayan, Ranjani and Gopalan, Nandhini (2014) Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 258-263.
Merchant, Farhad and Maity, Arka and Mahadurkar, Mahesh and Vatwani, Kapil and Munje, Ishan and Krishna, Madhava and Nalesh, S and Gopalan, Nandhini and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2015) Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 153-158.
Merchant, Farhad and Vatwani, Tarun and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, S K and Narayan, Ranjani (2018) Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 29 (8). pp. 1707-1720.
Merchant, Farhad and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2017) Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. In: Parallel Processing Letters, 27 (3-4). ISSN 0129-6264
Das, Saptarsi and Madhu, Kavitha and Krishna, Madhav and Sivanandan, Nalesh and Merchant, Farhad and Natarajan, Santhi and Biswas, Ipsita and Pulli, Adithya and Nandy, SK and Narayan, Ranjani (2014) A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. In: JOURNAL OF SYSTEMS ARCHITECTURE, 60 (7). pp. 592-614.
