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Conference Proceedings

Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-efficient redundant execution for chip multiprocessors. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI (GLSVLSI '10), May 16-18, 2010, Brown University Campus, Providence, Rhode Island, USA.

Conference Paper

Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding. In: IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), JUN 28-JUL 01, 2010, Chicago, IL,, pp. 121-130.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power during SoC Test. In: IEEE European Test Symposium (ETS) , May 2009.

Vayrynen, Mikael and Singh, Virendra and Larsson, Erik (2009) Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on Chips. In: International Conference on Design Automation and Test in Europe (DATE), Nice, 20-24 April 2009 , Nice.

Vinay, NS and Larsson, Erik and Singh, Virendra (2009) Thermal Aware Test Methodology of 3-D Integrated SoC. In: Workshop on 3-D Integration: Architecture, Design and Test (in conjunction with DATE’09), Apr 2009.

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Singh, Adit (2009) Capture Power Reduction for Modular System-on-Chip Test. In: 14th IEEE VLSI Design and Test Symposium (VDAT), Bangalore.

Tudu, Jaynarayan T and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power for Scan Circuit during Test. In: 14th IEEE European Test Symposium (EST 2009), May 25-29, 2009, Seville, SPAIN, pp. 25-30.

Singh, Virendra and Larsson, Erik (2008) On Reduction of Capture Powerfor Modular System-on-Chip Test. In: IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, JAPAN, November 27-28, 2008, November 27-28, 2008, Sapporo.