|
 | Up a level |
Vaswani, Kapil and Thazhuthaveetil, Matthew J and Srikant, YN and Joseph, PJ (2007) Microarchitecture sensitive empirical models for compiler optimizations. In: 5th International Symposium on Code Generation and Optimization, MAR 11-14, 2007, San Jose, CA.
Joseph, PJ and Vaswani, Kapil and Thazhuthaveetil, Matthew J (2006) A Predictive Perfomance Model for Superscalar Processors. In: 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006. MICRO-39., Dec. 2006 , Orlando, FL .
Joseph, PJ and Vaswani, Kapil and Thazhuthaveetil, Matthew J (2006) Construction and use of linear regression models for processor performance analysis. In: 12th International Symposium on High-Performance Computer Architecture,, Feb 11-15, 2006, Austin,TX,, pp. 99-108.
Joseph, PJ and Jacob, Matthew T (2003) Analysis of Control Flow Patterns in the Execution of SPEC CPU2000 Benchmark Programs. In: Conference on Convergent Technologies for the Asia-Pacific Region: IEEE TENCON 2003, 15-17 October, 2003, Bangalore, India, Vol.3 1143-1147.
Vajapeyam, Sriram and Joseph, PJ and Mitra, Tulika (1999) Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs. In: 26th International Symposium on Computer Architecture, 1999, 2-4 May, Atlanta,Georgia, 16 -27.
Joseph, PJ and Vajapeyam, Sriram (1996) Program-Level Control of Network Delay for Parallel Asynchronous Iterative Applications. In: 3rd International Conference on High Performance Computing, 1996, 19-22 December, Trivandrum,India, pp. 88-93.
