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Chaporkar, P and Kuri, J (2002) A network architecture for providing per-flow delay guarantees with scalable core. In: Journal of High Speed Networks, 12 (3-4). pp. 87-109.
Diwan, Aniruddha S and Guerin, Roch and Sivarajan, Kumar N (2001) Performance analysis of speeded-up high-speed packet switches. In: Journal of High Speed Networks, 10 (3). pp. 161-186.
