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Siddhu, Lokesh and Mishra, Amit and Singh, Virendra (2014) Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design. In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 483-488.
Prasanth, V and Singh, Virendra and Parekhji, Rubin (2012) Derating Based Hardware Optimizations in Soft Error Tolerant Designs. In: 30th IEEE VLSI Test Symposium (VTS), APR 23-25, 2012, Hawaii, USA, pp. 282-287.
Singh, Virendra and Fujita, Masahiro (2011) “Post silicon debug of SOC designs”. In: 2011 IEEE International SOC Conference (SOCC), 26-28 Sept. 2011, Taipei, p. 18.