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Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.
Kala, S and Nalesh, S and Maity, Arka and Nandy, SK and Narayan, Ranjani (2013) High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-23, 2013, Beijing, PEOPLES R CHINA, pp. 3034-3037.
Das, Saptarsi and Narayan, Ranjani and Narayan, Soumitra Kumar (2012) Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. In: 8th International Joint Conference on e-Business and Telecommunications, JUL 18-21, 2011, Seville, SPAIN , pp. 249-263.
Das, Saptarsi and Varadarajan, Keshavan and Garga, Ganesh and Mondal, Rajdeep and Narayan, Ranjani and Nandy, SK (2011) A method for flexible reduction over binary fields using a field multiplier. In: SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, 18-21 July, Seville, Spain.
Merchant, Farhad and Maity, Arka and Mahadurkar, Mahesh and Vatwani, Kapil and Munje, Ishan and Krishna, Madhava and Nalesh, S and Gopalan, Nandhini and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2015) Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 153-158.
