Scheduling expression trees with register variables on delayed-load architectures

Venugopal, R and Srikant, YN (1994) Scheduling expression trees with register variables on delayed-load architectures. In: Microprocessing & Microprogramming, 40 (8). pp. 577-596.

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Abstract

In this paper, we describe an optimal, linear time instruction scheduling algorithm for scheduling expression trees on delayed-load architectures with unit latency times. The algorithm is a generalization of the algorithm due to Proebsting and Fischer and handles expression trees with register variables. Register variables are useful in code generation across basic block boundaries and in code generation from DAGs. Register allocation is integrated with instruction scheduling. Spilling is handled optimally. The algorithm acts as a good heuristic for longer latency times and in code generation from DAGs.

Item Type:	Journal Article
Publication:	Microprocessing & Microprogramming
Publisher:	Elsevier
Additional Information:	The copyright of this article belongs to Elsevier.
Keywords:	Expression trees;Delayed-load architectures;Instruction scheduling;Pipeline scheduling;Code generation
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	04 Jul 2006
Last Modified:	19 Sep 2010 04:29
URI:	http://eprints.iisc.ac.in/id/eprint/7837

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