Architecture of Reconligurable a Low Power Gigabit ATM Switch

Lele, Abhijit M and Nandy, SK (2001) Architecture of Reconligurable a Low Power Gigabit ATM Switch. In: Fourteenth International Conference on VLSI Design, 2001, 3-7 January, Bangalore,India, 242 -247.

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Abstract

Multistage switch interconnects like banyan switches are preferred in high speed networks for their cascadable structure and suitability for VLSI implementation. However most of these switch implementations are monolithic in nature and do not provide flexibility of dynamic re-routing of cells from active ports through idle ports. In this paper we take a critical look at a basic $8\hspace{5mm}{\times}\hspace{5mm}8$ benes switch from the perspective of identifying smaller blocks which can be pipelined in space and temporally multiplexed to exploit hardware reuse. A topological analysis of a $8\hspace{5mm}{\times}\hspace{5mm}8$ benes switch is carried out to identify mutually exclusive path sets that can be overlayed for hardware reuse. Based on this analysis we arrive at a basic building block called X-Structure, using which a $8\hspace{5mm}{\times}\hspace{5mm}8$ switch is constructed. The X-structure supports dynamic re-routing of cells and power down mode. A communication controller is designed using the the X-Structure based ATM switch at its core. A performance evaluation of the switch indicates a power saving of $66.66\%$ due to hardware reuse, an $18.6\%$ increase in hardware utilization and an aggregate throughput of 2.66 Gbps for a $8\hspace{5mm}{\times}\hspace{5mm}8$ switch.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	15 Feb 2006
Last Modified:	19 Sep 2010 04:23
URI:	http://eprints.iisc.ac.in/id/eprint/5360

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