CMOS Op-Amp Sizing Using a Geometric Programming Formulation

Mandal, Pradip and Visvanathan, V (2001) CMOS Op-Amp Sizing Using a Geometric Programming Formulation. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20 (1). pp. 22-38.

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Abstract

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation

Item Type:	Journal Article
Publication:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Cell-generation;Device-models;Optimization;Transistor-sizing;VLSI
Department/Centre:	Division of Electrical Sciences
Date Deposited:	05 Feb 2007
Last Modified:	19 Sep 2010 04:23
URI:	http://eprints.iisc.ac.in/id/eprint/5308

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