Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA

Venkateshan, Sriram and Patel, Alap and Varghese, Kuruvilla (2015) Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23 (10). pp. 2221-2232.

PDF IEEE_Tra_on_Ver_Lar_Sca_Int_Sys_23-10_2221_2015.pdf - Published Version Restricted to Registered users only Download (3MB) | Request a copy

Abstract

Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, which can compute multiple rows of the kernel matrix in parallel. Further, we propose an extended variant of the popular decomposition technique, sequential minimal optimization, which we call hybrid working set (HWS) algorithm, to effectively utilize the benefits of cached kernel columns and the parallel computational power of the coprocessor. The coprocessor is implemented on Xilinx Virtex 7 field-programmable gate array-based VC707 board and achieves a speedup of upto 25x for kernel computation over single threaded computation on Intel Core i5. An application speedup of upto 15x over software implementation of LIBSVM and speedup of upto 23x over SVMLight is achieved using the HWS algorithm in unison with the coprocessor. The reduction in the number of iterations and sensitivity of the optimization time to variation in cache size using the HWS algorithm are also shown.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	Cache; FPGA; hardware-software codesign; hybrid working set (HWS); sequential minimal optimization (SMO); support vector machine (SVM)
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	03 Dec 2015 04:48
Last Modified:	03 Dec 2015 04:48
URI:	http://eprints.iisc.ac.in/id/eprint/52848

Actions (login required)

View Item