A novel path delay fault simulator using binary logic

Majhi, AK and Jacob, J and Patnaik, LM (1996) A novel path delay fault simulator using binary logic. In: VLSI Design, 4 (3). pp. 167-179.

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Abstract

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V1, V2>, while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm.

Item Type:	Journal Article
Publication:	VLSI Design
Publisher:	Gordon & Breach
Additional Information:	Copyright of this article belongs to Gordon & Breach.
Keywords:	combinational circuits;delays;fault diagnosis;logic CAD
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	29 Aug 2007
Last Modified:	09 Jan 2012 09:53
URI:	http://eprints.iisc.ac.in/id/eprint/10747

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