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All-Digital Synchronizers For DPSK Demodulators

Jamadagni, HS and Sonde, BS and Shah, AV (1990) All-Digital Synchronizers For DPSK Demodulators. In: International Zurich Seminar on Digital Communications, 1990. 'Electronic Circuits and Systems for Communications', 5-8 March, Zurich, pp. 268-283.

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Abstract

Bit synchronization is an important operation used at the receiving end of synchronous communication systems for providing a reference bit clock to the receiver; this reference marks the instants at which transition in data bits occur at the transmitting end. In some DPSK demodulator realizarions, like the integrate-and-dump scheme, the bit clock is essential for & a recovery itself. But in most demodulators the bit clock is required just for "cleaning up" the demodulated data and to provide an output with uniform data widths. Generally this is done by sampling the demodulator output (called the "raw data") with another clock, which is in phase opposition with respect to the bit clock. Instants at which the bit clock transitions have to occur at the receiver and which are not a prwri known to the receiver, are rcsually estimated based on transitions of the received data. Such estimators are commonly realized as phase locked loops (PLL) with data transitions as reference inpis. In the presence of noise in the communication channel, transitions of bit clock waveform produced by the receiver synchronizer do not occur at exactly uniform intervals, but will have a random fluctuation, called the jitter, associated with them. Hence, cleaning up the demodulator output with the bit clock introduces some additional errors into the demodulated data and thus degrades the bit-error rate (BER) performance of the demodulator. In this paper, Maimurn-A Posteriori (MAP) and Data Transition Tracking Loop (DTTL) synchronizers are developed for the DPSK scheme. In their original form, these synchronizers require substantial hardware for their realization. By some simplifications, hardware complexity is considerably reduced and simplified "all-digital" MAP and DlTL synchronizers are suggested. The hardware needed to realize these schemes is not significantly more than that required for the simple early-late scheme, Results of computer simulation studies on all digital MAP and DlTL synchronizers are given. They not only indicate that the degradation in the BER performance of the demodulator due to these synchronizers is about 02 d6, as compared to I to 2 dB for the simple early-late scheme, but also that the MAP and DlTL schemes have much lower jitter. Results of an experimental study on microprocessor-based hardware realizations of the synchronizers are given. The circuits developed are suitable for the realization of a digital IC for synchronization as well as in DPSK Modems.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Depositing User: Lourdu Raj M Arockia
Date Deposited: 30 May 2006
Last Modified: 19 Sep 2010 04:27
URI: http://eprints.iisc.ac.in/id/eprint/7068

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