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Low-Power Configurable Processor Array for DLMS Adaptive Filtering

Ramanathan, S and Visvanathan, V (1997) Low-Power Configurable Processor Array for DLMS Adaptive Filtering. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 198 -203.

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Abstract

In this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is then extended to derive a configurable processor array (CPA), which is configurable for filter order, sample period and power reduction factor. The hardware overhead incurred for configurability is minimal.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Depositing User: HS Usha
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:25
URI: http://eprints.iisc.ac.in/id/eprint/6422

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