ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

A Floating-point Validation Suite for High-performance Shared and Distributed Memory Computing Systems

Ghoshal, SK (1997) A Floating-point Validation Suite for High-performance Shared and Distributed Memory Computing Systems. In: Fourth International Conference on High Performance Computing, 1997, 18-21 December, Bangalore,India, 88 -93.

[img]
Preview
PDF
a_floating.pdf

Download (453kB)

Abstract

A methodology to systematically identify and isolate bugs in floating point implementation in high performance multiple CPU computing systems is formulated. A validation suite is written and tested. Results show improper implementation. Proper implementation guidelines are suggested and prototyped.

Item Type: Conference Paper
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: IEEE754;Validation;Suite;NaN
Department/Centre: Division of Interdisciplinary Research > Supercomputer Education & Research Centre
Depositing User: HS Usha
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:25
URI: http://eprints.iisc.ac.in/id/eprint/6411

Actions (login required)

View Item View Item