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Low-loss 7-bit S-band CMOS passive phase shifter with digital control

Kumar, Vijay and Garg, Divya Kumar and Selvaraja, Shankar Kumar and Saravanan, GSai and Kumar, MMadhava (2019) Low-loss 7-bit S-band CMOS passive phase shifter with digital control. In: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 47 (4). pp. 542-548.

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Official URL: https://doi.org/10.1002/cta.2600


This paper presents the design and implementation of a 7-bit S-band digital passive phase shifter using Complementary Metal-Oxide-Semiconductor (CMOS) 65-nm technology in 2.6- to 3.2-GHz frequency band. New switched delay network topology has been used for 5.625 degrees and 2.8 degrees, and modified switched filter topology has been used for implementation of other phase bits to achieve 7-bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7-bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0 degrees, average RMS amplitude error of less than 0.6 dB, input matching (S-11) better than -7.5 dB, and output matching (S-22) better than -14.5 dB across the target frequency band at 50 omega input/output impedance.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Keywords: MOS switch; passive phase shifter; phase; RMS; S-band
Department/Centre: Division of Interdisciplinary Research > Centre for Nano Science and Engineering
Depositing User: Id for Latest eprints
Date Deposited: 23 May 2019 10:11
Last Modified: 23 May 2019 10:11
URI: http://eprints.iisc.ac.in/id/eprint/62633

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