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Effect of substrate transfer on performance of vertically stacked ultrathin MOS devices

Nittala, PVK and Sahoo, K and Bhat, N and Bhat, KN and Sen, P (2019) Effect of substrate transfer on performance of vertically stacked ultrathin MOS devices. In: IEEE Transactions on Electron Devices, 66 (3). pp. 1153-1159.

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Official URL: https://dx.doi.org/10.1109/TED.2019.2893653

Abstract

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator(SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of �1.4 μm was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold-indium (Au-In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal-oxide-semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. © 2019 IEEE.

Item Type: Journal Article
Additional Information: copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords: Gold alloys; Indium alloys; Metals; MOS devices; MOSFET devices; Oxide semiconductors; Silicon on insulator technology; Silicon wafers; Substrates; Temperature, 3-D integration; Electrical characterization; Layer transfer; Low- temperature process; Silicon on insulator wafers; Silicon substrates; Silicon-on- insulators (SOI); Transient liquid phase bonding, Wafer bonding
Department/Centre: Division of Interdisciplinary Research > Centre for Nano Science and Engineering
Depositing User: Id for Latest eprints
Date Deposited: 08 Apr 2019 11:19
Last Modified: 08 Apr 2019 11:19
URI: http://eprints.iisc.ac.in/id/eprint/62000

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